The present invention relates to a semiconductor variable capacitor and a method of manufacturing the same, more specifically, a semiconductor variable capacitor including a carrier removal terminal which, upon the application of an inversion bias, extracts carriers induced in an inversion layer formed below a gate insulating layer, and a method of manufacturing the semiconductor variable capacitor.
Semiconductor variable capacitors are incorporated in semiconductor integrated circuits as the oscillation frequency control devices of, e.g., voltage controlled oscillators (VOC). The semiconductor variable capacitors are junction capacitors, inversion mode MOS capacitors, accumulation mode MOS capacitors, etc. With the recent signaling speed increase, the semiconductor variable capacitors using the accumulation mode MOS capacitors, which are good in the high-frequency characteristics, are increasingly used.
FIG. 23 is a diagrammatic sectional view showing the structure of the conventional accumulation mode MOS type semiconductor variable capacitor.
In a semiconductor substrate 100, a device isolation film 102 for defining an active region is formed. In the semiconductor substrate 100 in the active region, an n-well 104 is formed. Over the semiconductor device in the active region 104, a gate electrode 108 is formed with a gate insulating film 106 interposed therebetween. In the active region on both sides of the gate electrode 108, an n-type source region 110 and an n-type drain region 112 are formed.
The semiconductor variable capacitor shown in FIG. 23 has a structure similar to that of the usual NMOS transistor but is characterized by being formed not in a p-well but in an n-well. The source region 110 and the drain region 112 are electrically connected to each other and operate as a two-terminal element of the gate electrode 108 and the source/drain regions 110, 112.
When a positive voltage is applied to the gate electrode 108, an electron accumulation layer is formed in the upper surface of the semiconductor substrate 100, and the capacitance between the gate electrode 108 and the source/drain regions 110, 112 increases. The usual NMOS transistor structure (inversion mode MOS capacitor), in which an inversion layer of electrons is formed in the upper surface of the semiconductor substrate, has the capacitance value equivalent to that of the accumulation mode, but has high channel resistance and high-frequency characteristics which are inferior to the accumulation mode. When a negative voltage is applied to the gate electrode 108, a depletion layer expands in the surface of the semiconductor substrate 100, and the capacitance between the gate electrode 108 and the source/drain regions 110, 112 becomes small.
FIGS. 24A and 24B are C-V characteristics of the accumulation mode MOS capacitor type semiconductor variable capacitor prepared under process conditions for the 3.3-voltage transistor. FIG. 24A shows the characteristics of all the sweep range of applied voltage, and FIG. 24B expands the characteristics of the negative voltage side. In FIGS. 24A and 24B, the ▪ marks indicate the case that the voltage was swept from the negative side to the positive side, and the ▴ marks indicate the case that the voltage was swept from the positive side to the negative side.
As shown in FIG. 24B, in the region where the gate voltage is not more than −1 V, the capacitance value varies depending on the sweep mode. That is, when the gate voltage is swept from negative to positive, the capacitance values tend to be a little large, and when the gate voltage is swept from positive to negative, the capacitance value tends to be a little small. This is due to that the inversion layer of holes is formed in the upper surface of the semiconductor substrate.
FIG. 25 is an energy band diagram given when a negative voltage is applied to the gate electrode, and the inversion layer of holes is formed in the upper surface of the semiconductor substrate. Because of no connection terminal for these holes, even when the gate voltage is changed, the hole concentration does not instantaneously change. The hole concentration slowly change over several seconds or several minutes by the generation of electrons and holes and the recombinations which spontaneously take place. When the hole concentration is low, the depletion layer of the n-well expands, and the capacitance decreases, and when the hole concentration is high, the depletion layer of the n-well reduces, and the capacitance increases, with the result that the capacitance value slowly change corresponding to the hole concentrations. Accordingly, the capacitance value has an uncertain component which depends on a history of a voltage applied to the gate, and the magnitude is even about 5-10% of the capacitance value as seen in FIG. 24B. The oscillation frequency of the VCO is determined by the capacitance value of the semiconductor variable capacitor, and the uncertain capacitance component is a large problem for the circuit design.
As means of solving this problem, it is proposed to provide a terminal for removing the holes.
FIG. 26 is a diagrammatic sectional view showing the structure of the semiconductor variable capacitor including a terminal for removing holes.
In a p-type semiconductor substrate 100, an n-well 104 is formed. Over the semiconductor substrate 100 in the region where the n-well 104 is formed, a gate electrode 108 is formed with a gate insulating film 106 interposed therebetween. In the semiconductor substrate 100 on both sides of the gate electrode 108, a p-type source region 110 and a p-type drain region 112 are formed. In the n-well 104, an n-type contact region 114 is formed. In the semiconductor substrate 100, a p-type contact region 116 is formed.
The semiconductor variable capacitor shown in FIG. 26 has the same structure as the usual PMOS transistor and uses as a variable capacitor a capacitor including the gate electrode 108/the gate insulating film 106/the N-well 104, and uses as a hole removal terminal the source/drain regions 110,112.
However, in the conventional semiconductor variable capacitor shown in FIG. 26, when the electron accumulation layer is formed in the surface of the semiconductor substrate 100 by applying a positive voltage to the gate electrode 108, the parasitic resistance becomes large because of the n-type contact region 114 being remote from the electron accumulation layer, and high-frequency characteristics are degraded.
In this structure, a p-type dopant is implanted in the gate electrode 108 of polycrystalline silicon in the usual processing, and the structure of the p+ polycrystalline silicon/the gate insulating film/the n-well is formed. Accordingly, to form the electron accumulation layer, a relatively high voltage must be applied to the gate electrode 108 in comparison with the structure of the usual n+ polycrystalline silicon/the gate insulating film/the n-well.